The cost per bit of magnetic memory, such as magnetic disks, is decreasing. However, the cost per bit of nonvolatile memory, such as EEPROMs, is decreasing at an even faster rate. Presently, most systems do not employ nonvolatile devices due to their limited endurance, which in the best EEPROM technologies is at most approximately 10.sup.7 erase/write cycles. This is due to the breakdown of tunneling dielectrics. When nonvolatile devices are employed, severe limitations are placed on the circuit design. Specifically, such a system must be configured to limit the number of erase/write cycles experienced by the nonvolatile devices. The following are examples of such systems.
U.S. Pat. No. 4,803,707 to Cordan Jr. discloses a vehicle odometer system for counting pulses representing vehicle mileage, and for storing the signal count during periods when the vehicle power is disabled. In this system, a group of nonvolatile memory cells is used to store binary values for odometer readings up to 10,000 miles. For odometer readings greater than 10,000, a new set of memory cells is accessed. Thus, each group of memory cells is cycled up to only 10,000 times which is below the endurance limit. The higher order bits of each memory block, which are not cycled as often as the lower-order bits, serve as a pointer for the new set of memory cells.
In order to ensure the integrity of the stored data, this system requires that each group of nonvolatile memory cells be reallocated well below the maximum endurance limit of the cells. However, such a reallocation scheme is not practical in a system containing a large number memory blocks because the memory blocks would be reallocated too often.
U.S. Pat. No. 4,528,683 to Henry discloses an odometer system which employs a highly particularized five-bit word per decimal position counting scheme, along with a multi-level multiplexer to move the decimal ones, tens, hundreds and thousands position through a nonvolatile memory array. This system allows erase/cycle "wear" effects of the cells to be spread throughout the memory array, thereby preventing any one group of cells from wearing out too quickly.
U.S. Pat. No. 4,663,770 to Murray et al discloses a system including nonvolatile counter devices. In order to distribute the erase/write cycle wear effects among the various counter devices, counter usage is successively shifted. While the scheme of this system allows for distribution of the erase/write wear effects among the nonvolatile devices within the system, the coding and decoding for this distribution requires a complex hardware configuration.